1. Field of the Invention
The present invention relates to a data processor in general, and in particular to a memory control system for a data processor for effectively processing an address boundary in a main memory unit.
In the field of data processing, the minimum unit of data bit length processed in an arithmetic control unit is defined as one address of the main memory unit. However, data practically processed in the arithmetic control unit frequently has a data length n times as long as the minimum unit length, n being an integer.
In a data processor in which the access unit length of data to the main memory is different from the processing unit length of an instruction word and data, an address boundary between full word data and half-word data in the main memory unit must be processed in some way. Many proposals for such address boundary processing have been made. In medium- and large-scale computers, a buffer memory is used as a means for high speed data processing. For this, address boundary processing in the form of hardware is frequently needed in a control section to control the buffer memory. For example, "COMPUTER ORGANIZATION" by Ivan Flores, 1969 describes on pages 262 to 272 an instruction readout processing method in connection with a relation of an instruction word length to a predetermined memory boundary.
In a small-scale computer, a buffer memory control section is undesirable since it introduces complexity and expense into the control section. To avoid this, the following measures have heretofore been taken in this type computer. (1). A restriction is placed on the position of the operand of an instruction stored in the main memory and the position of transaction data. (2). The operand data extending over an address boundary is reconstructed in the arithmetic control unit and then is processed.
Both measures, however, provide poor operating efficiency.